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data sheet ics810251agi revision b october 5, 20 12 1 ?2012 integrated device technology, inc. vcxo and synchronous ethernet jitter attenuator ics810251i general description the ics810251i is a high performance, low jitter/low phase noise vcxo. the ics810251i uses a low frequency and low cost pullable crystal to achieve jitter attenuation for synchronous ethernet applications. the ics810251i can take an input of either 25mhz or 125mhz and produce a single lvcmos output of 25mhz. the device is packaged in a small 16 lead tssop package and is ideal for use on space constrained boards typically encountered in most synchronous ethernet applications. applications ? synchronous ethernet v0.39a ? end equipment compliant with std ieee 802.039a features ? one single-ended output (lvcmos or lvttl levels), output impedance: 15 ? ? phase jitter attenuation by th e vcxo-pll using a 25mhz pullable external crystal (xtal) ? input frequencies: 25mhz or 125mhz ? output frequency: 25mhz ? pll loop bandwidth adjustable by external components ? 25mhz or 125mhz auto input frequency detect ? full 3.3v or 2.5v supply voltage ? -40c to 85c ambient operating temperature ? available in lead-free (rohs 6) package ics810251i 16-lead tssop 4.4mm x 5.0mm x 0.925mm package body g package top view pin assignment block diagram vcxo-pll lf0 lf1 (external loop filter inputs.) xtal_in xtal_out pre- divider pfd cp vcxo 25mhz 25mhz clk_in q (25mhz or 125mhz input frequency auto detect) (1 or 5) oe 1 0 pll_sel 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 oe q reserved gnd pll_sel clk_in lf1 lf0 gnd xtal_in xtal_out g n d v ddo v dda v dd v dd
ics810251i data sheet vcxo and synchronous ethernet jitter attenuator ics810251agi revision b october 5, 20 12 2 ?2012 integrated device technology, inc. table 1. pin descriptions note: pullup and pulldown refer to internal input resistors. see table 2, pin characteristics, for typical values. table 2. pin characteristics number name type description 1 pll_sel input pullup when logic high, the vcxo-pll is enabled. when low, the vcxo-pll is in bypass mode. lvcmos/lvttl interface levels. 2, 9, 12 gnd power power supply ground. 3 reserved reserved reserved pin. do not connect. 4 q output single-ended clock output. lvcmos/ lvttl interface levels. 5v ddo power output power supply pin. 6 oe input pullup output enable pin for q output. lvcmos/lvttl interface levels. 7v dda power analog supply pin. 8, 15 v dd power core supply pins. 10, 11 xtal_out, xtal_in input vcxo crystal oscillator interface. xtal_i n is the input. xtal_out is the output. 13, 14 lf0, lf1 analog input/ output loop filter connection node pins. 16 clk_in input pulldown single-ended clock input. lvcmos/lvttl interface levels. symbol parameter test conditions minimum typical maximum units c in input capacitance 4pf c pd power dissipation capacitance v dd, v ddo = 3.465v 8 pf v dd, v ddo = 2.625v 5 pf r pullup input pullup resistor 51 k ? r pulldown input pulldown resistor 51 k ? r out output impedance v ddo = 3.3v5% 15 ? v ddo = 2.5v5% 20 ?
ics810251i data sheet vcxo and synchronous ethernet jitter attenuator ics810251agi revision b october 5, 20 12 3 ?2012 integrated device technology, inc. absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only . functional operation of product at t hese conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. dc electrical characteristics table 3a. power supply dc characteristics, v dd = v ddo = 3.3v 5%, t a = -40c to 85c table 3b. power supply dc characteristics, v dd = v ddo = 2.5v 5%, t a = -40c to 85c item rating supply voltage, v dd 4.6v inputs, v i -0.5v to v dd + 0.5v outputs, v o -0.5v to v dd + 0.5v package thermal impedance, ? ja 92.4 ? c/w (0 mps) storage temperature, t stg -65 ? c to 150 ? c symbol parameter test conditio ns minimum typical maximum units v dd core supply voltage 3.135 3.3 3.465 v v dda analog supply voltage v dd ? 0.07 3.3 v dd v v ddo output supply voltage 3.135 3.3 3.465 v i dd power supply current 40 ma i dda analog supply current 7ma i ddo output supply current no load 5 ma symbol parameter test conditio ns minimum typical maximum units v dd core supply voltage 2.375 2.5 2.625 v v dda analog supply voltage v dd ? 0.07 2.5 v dd v v ddo output supply voltage 2.375 2.5 2.625 v i dd power supply current 35 ma i dda analog supply current 7ma i ddo output supply current no load 5 ma
ics810251i data sheet vcxo and synchronous ethernet jitter attenuator ics810251agi revision b october 5, 20 12 4 ?2012 integrated device technology, inc. table 3c. lvcmos/lvttl dc characteristics, v dd = v ddo = 3.3v 5% or 2.5v 5%, t a = -40c to 85c note 1: outputs terminated with 50 ? to v ddo /2. see parameter measurement information section. load test circuit diagrams. ac electrical characteristics table 4a. ac characteristics, v dd = v ddo = 3.3v 5%, t a = -40c to 85c note: electrical parameters are guaranteed over the specified am bient operating temperature rang e, which is established when de vice is mounted in a test socket with maintained transverse airflow great er than 500 lfpm. device will meet specifications after therma l equilibrium has been reached under these conditions. note: characterized using a 616hz bandwidth filter. note 1: this parameter is defined in accordance with jedec standard 65. note 2: please refer to the phase noise plot. note 3: specified with the vcxo-pll free running high. note 4: specified with the vcxo-pll locked. symbol parameter test conditio ns minimum typical maximum units v ih input high voltage v dd = 3.465v 2 v dd + 0.3 v v dd = 2.625v 1.7 v dd + 0.3 v v il input low voltage v dd = 3.465v -0.3 0.8 v v dd = 2.625v -0.3 0.7 v i ih input high current clk_in v dd = v in = 3.465v or 2.625v 150 a oe, pll_sel v dd = v in = 3.465v or 2.625v 5 a i il input low current clk_in v dd = 3.465v or 2.625v, v in = 0v -5 a oe, pll_sel v dd = 3.465v or 2.625v, v in = 0v -150 a v oh output high voltage; note 1 v ddo = 3.3v 5% 2.6 v v ddo = 2.5v 5% 1.8 v v ol output low voltage; note 1 v ddo = 3.3v 5% 0.6 v v ddo = 2.5v 5% 0.5 v symbol parameter test conditions minimum typical maximum units f ref input reference frequency 25 mhz 125 mhz f vco vcxo-pll frequency 25 mhz f out output frequency 25 mhz t jit(cc) cycle-to-cycle jitter; note 1 45 ps tjit( ? ) rms phase jitter (random); note 2 f out = 25mhz, integration range: 1khz ? 1mhz 0.22 ps t jit(per) period jitter 5ps t r / t f output rise/fall time 20% to 80% 500 1200 ps odc output duty cycle; note 3 48 52 % odc output duty cycle; note 4 45 55 %
ics810251i data sheet vcxo and synchronous ethernet jitter attenuator ics810251agi revision b october 5, 20 12 5 ?2012 integrated device technology, inc. table 4b. ac characteristics, v dd = v ddo = 2.5v 5%, t a = -40c to 85c note: electrical parameters are guaranteed over the specified am bient operating temperature rang e, which is established when de vice is mounted in a test socket with maintained transverse airflow great er than 500 lfpm. device will meet specifications after therma l equilibrium has been reached under these conditions. note: characterized using a 616hz bandwidth filter. note 1: this parameter is defined in accordance with jedec standard 65. note 2: please refer to the phase noise plot. note 3: specified with the vcxo-pll free running high. note 4: specified with the vcxo-pll locked. symbol parameter test condition s minimum typical maximum units f ref input reference frequency 25 mhz 125 mhz f vco vcxo-pll frequency 25 mhz f out output frequency 25 mhz t jit(cc) cycle-to-cycle jitter; note 1 35 ps tjit rms phase jitter (random); note 2 f out = 25mhz, integration range: 1khz ? 1mhz 0.24 ps t jit(per) period jitter 10 ps t r / t f output rise/fall time 20% to 80% 700 2200 ps odc output duty cycle; note 3 48 52 % odc output duty cycle; note 4 44 56 %
ics810251i data sheet vcxo and synchronous ethernet jitter attenuator ics810251agi revision b october 5, 20 12 6 ?2012 integrated device technology, inc. typical phase noise at 25mhz (3.3v) typical phase noise at 25mhz (2.5v) ethernet filter phase noise result by adding an ethernet filter to raw data raw phase noise data 25mhz rms phase jitter (random) 1khz to 1mhz = 0.22ps (typical) noise power dbc hz offset frequency (hz) 25mhz rms phase jitter (random) 1khz to 1mhz = 0.24ps (typical) noise power dbc hz offset frequency (hz)
ics810251i data sheet vcxo and synchronous ethernet jitter attenuator ics810251agi revision b october 5, 20 12 7 ?2012 integrated device technology, inc. parameter measureme nt information 3.3v core/3.3v lvcmos output load ac test circuit cycle-to-cycle jitter period jitter 2.5v core/2.5v lvcmos output load ac test circuit rms phase jitter output rise/fall time scope qx gnd v dd, 1.65v?5 -1.65v?5 v ddo v dda 1.65v?5 ? ? ? ? v ddo 2 v ddo 2 v ddo 2 t cycle n t cycle n+1 t jit(cc) = | t cycle n ? t cycle n+1 | 1000 cycles q v oh v ref v ol mean period (first edge after trigger) reference point (trigger edge) 1 contains 68.26% of all measurements 2 contains 95.4% of all measurements 3 contains 99.73% of all measurements 4 contains 99.99366% of all measurements 6 contains (100-1.973x10 -7 )% of all measurements histogram scope qx gnd v dd, 1.25v?5 -1.25v?5 v ddo 1.25v?5 v dda phase noise mask offset frequency f 1 f 2 phase noise plot rms jitter = area under the masked phase noise plot noise power 20% 80% 80% 20% t r t f q
ics810251i data sheet vcxo and synchronous ethernet jitter attenuator ics810251agi revision b october 5, 20 12 8 ?2012 integrated device technology, inc. parameter measurement in formation, continued output duty cycle/pulse width/period application information recommendations for unused input pins inputs: lvcmos control pins all control pins have internal pull-ups or pull-downs; additional resistance is not required but ca n be added for additional protection. a 1k ? resistor can be used. t period t pw t period odc = v ddo 2 x 100% t pw q
ics810251i data sheet vcxo and synchronous ethernet jitter attenuator ics810251agi revision b october 5, 20 12 9 ?2012 integrated device technology, inc. schematic example figure 1 shows an example of the 810251i application schematic. in this example, the device is operated either at v dd = 3.3v or 2.5v. the decoupling capacitors should be located as close as possible to the power pin. the input is driven by an lvcmos driver. an optional 3-pole filter can also be used for additional spur reduction. it is recommended that the loop filter components be laid out for the 3-pole option. this will also allo w the 2-pole filter to be used. figure 1. p.c. ics810251i schematic example cp 0.001 uf lf1 rd1 not install ru1 1k logic control input examples vdd cp tbd to logic input pins zo = 50 r3 tbd set logic input to '1' cs tbd r2 10 lf0 vdd vddo vdd c30 0.01u lvcmos_receiv er r1 33 rs tbd vdd q1 lvcmos_driv er xta l _ i n c2 0.1u set logic input to '0' x2 c6 spare xta l _ o u t to logic input pins c5 spare u1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 pll_sel gnd reserv ed q vddo oe vdda vdd gnd xta l _ o u t xta l _ i n gnd lf0 lf1 vdd clk_in c4 0.1u 3-pole loop filter example - (optional) c3 tbd cs 10uf c1 0.1u vdda rs 1k vdd vdd=vddo=3.3v rd2 1k zo = 50 c45 10u r4 33 ru2 not install 2-pole loop filter
ics810251i data sheet vcxo and synchronous ethernet jitter attenuator ics810251agi revision b october 5, 2012 10 ?2012 integrated device technology, inc. vcxo-pll e xternal c omponents choosing the correct external components and having a proper printed circuit board (pcb) layout is a key task for quality operation of the vcxo-pll. in choosing a cryst al, special precaution must be taken with the package and load capacitance (c l ). in addition, frequency, accuracy and temperature range must also be considered. since the pulling range of a crystal also varies with the package, it is recommended that a metal-canned package like hc49 be used. generally, a metal-canned package has a larger pulling range than a surface mounted device (smd). for crystal selection information, refer to the vcxo crystal selection application note. the crystal?s load capacitance c l characteristic determines its resonating frequency and is closely related to the vcxo tuning range. the total external capacitance seen by the crystal when installed on a board is the sum of the stray board capacitance, ic package lead capacitance, internal varactor capacitance and any installed tuning capacitors (c tune ). if the crystal c l is greater than the total external capacitance, the vcxo will oscillate at a higher frequency than the crystal specification. if the crystal c l is lower than the total external capacitance, the vcxo will oscillate at a lower frequency than the crystal specification. in either case, the absolute tuning range is reduced. the correct value of c l is dependant on the characteristics of the vcxo. the recommended c l in the crystal parameter table balances the tuning range by centering the tuning curve. the frequency of oscillation in the third overtone mode is not necessarily at exactly three time s the fundamental frequency. the mechanical properties of the quartz element dictate the position of the overtones relative to the fundamental. the oscillator circuit may excite both the fundamental and overtone modes simultaneously. this will cause a nonlinearity in the tuning curve. this potential problem is why vcxo crystals are required to be tested for absence of any activity inside a +/-200 ppm window at three times the fundamental frequency. refer to f l_3ovt and f l_3ovt_spurs in the crystal characteristics table. the crystal and external loop filter components should be kept as close as possible to the device. loop filter and crystal traces should be kept short and separated from each other. other signal traces should be kept separate and not run underneath the device, loop filter or crystal components. vcxo characteristics table vcxo-pll loop bandwidth selection table crystal characteristics lf0 lf1 xtal_in xtal_out r s c s c p c tune c tune 25mhz symbol parameter typical units k vcxo vcxo gain 15000 hz/v c v_low low varactor capacitance 9.8 pf c v_high high varactor capacitance 22.7 pf bandwidth crystal frequency (mhz) r s (k ? )c s (f) c p (f) 246hz (low) 25 0.4 10 0.01 616hz (mid) 25 1.0 10 0.001 1000hz (high) 25 1.65 10 0.001 symbol parameter test conditions minimum typical maximum units mode of oscillation fundamental f n frequency 25 mhz f t frequency tolerance 20 ppm f s frequency stability 20 ppm operating temperature range -40 +85 0 c c l load capacitance 10 pf c o shunt capacitance 4 pf c o / c 1 pullability ratio 220 240 esr equivalent series resistance 20 ? drive level 1mw aging @ 25 0 c 3 per year ppm
ics810251i data sheet vcxo and synchronous ethernet jitter attenuator ics810251agi revision b october 5, 2012 11 ?2012 integrated device technology, inc. power considerations this section provides information on power dissipation and junction temperature for the ics810251i. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ics810251i is the sum of th e core power plus the analog power plus the power dissipated in the load(s). the following is the power dissipation for v dd = 3.3v + 5% = 3.465v, which gives worst case results. ? power (core) max = v dd_max * (i dd + i dda + i ddo ) = 3.465v *(40ma + 7ma + 5ma) = 180.18mw ? output impedance r out power dissipation due to loading 50 ? to v dd /2 output current i out = v dd_max / [2 * (50 ? + r out )] = 3.465v / [2 * (50 ? + 15 ? )] = 26.7ma ? power dissipation on the r out per lvcmos output power (r out ) = r out * (i out ) 2 = 15 ? * (26.7ma) 2 = 10.7mw per output dynamic power dissipation at 25mhz power (25mhz) = c pd * frequency * (v dd ) 2 = 8pf * 25mhz * (3.465v) 2 = 2.4mw per output total power dissipation ? total power = power (core) max + power (r out ) + power (25mhz) = 180.18mw + 10.7mw + 2.4mw = 193.28mw 2. junction temperature. junction temperature, tj, is the temperature at the junction of the bond wire and bond pad and it directly affects the reliabil ity of the device. the maximum recommended junction temperature is 125c. limiting the in ternal transistor junction temperature, tj, to 125c ensures that the bond wire and bond pad temperature remains below 125c. the equation for tj is as follows: tj = ? ja * pd_total + t a tj = junction temperature ? ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ? ja must be used. assuming no air flow and a multi-layer board, the appropriate value is 92.4c/w per table 5 below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 0.193w *92.4c/w = 102.8c. this is well below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). table 5. thermal resistance ? ja for 16 lead tssop, forced convection ? ja by velocity meters per second 012.5 multi-layer pcb, jedec standard test boards 92.4c/w 88.0c/w 85.9c/w
ics810251i data sheet vcxo and synchronous ethernet jitter attenuator ics810251agi revision b october 5, 2012 12 ?2012 integrated device technology, inc. reliability information table 6. ? ja vs. air flow table for a 16 lead tssop transistor count the transistor count for ics810251i: 937 package outline and package dimensions package outline - g suffix for 16 lead tssop table 7. package dimensions for 16 lead tssop reference document: jedec publication 95, mo-153 ? ja vs. air flow meters per second 012.5 multi-layer pcb, jedec standard test boards 92.4c/w 88.0c/w 85.9c/w all dimensions in millimeters symbol minimum maximum n 16 a 1.20 a1 0.5 0.15 a2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 d 4.90 5.10 e 6.40 basic e1 4.30 4.50 e 0.65 basic l 0.45 0.75 ? 0 8 aaa 0.10
ics810251i data sheet vcxo and synchronous ethernet jitter attenuator ics810251agi revision b october 5, 2012 13 ?2012 integrated device technology, inc. ordering information table 8. ordering information part/order number marking package shipping packaging temperature 810251agilf 10251ail 16 lead ?lead-free? tssop tube -40 ? c to 85 ? c 810251AGILFT 10251ail 16 lead ?lead-free? tssop tape & reel -40 ? c to 85 ? c
ics810251i data sheet vcxo and synchronous ethernet jitter attenuator ics810251agi revision b october 5, 2012 14 ?2012 integrated device technology, inc. revision history sheet rev table page description of change date a t8 1 10 14 updated figure 1, schematic layout. vcxo-pll external components section, reworded second from last paragraph ?the frequency of oscillation in the third overtone mode....?. changed marking from 810251al to 10251al. changed datasheet header/footer format. 7/28/09 b t4a t4b 1 4 5 features list: deleted ?absolute pull range is 50 ppm (using the internal oscillator)? 3.3v ac characteristics table - added addit ional odc row with specs of 45min and 55max. added notes 3 & 4. 2.5v ac characteristics table - added addit ional odc row with specs of 44min and 56max. added notes 3 & 4. hiperclock references have been deleted throughout the datasheet. 7/17/2012 b t4a t4b t8 4 5 13 added ?high? to note 3. added ?high? to note 3. deleted quantity from tape and reel. 10/5/2012
ics810251i data sheet vcxo and sy nchronous ethernet jitter attenuator disclaimer integrated device technology, inc. (idt) and its subsidiaries reserve the ri ght to modify the products and/or specif ications described herein at any time and at idt? s sole discretion. all information in this document, including descriptions of product features and performance, is s ubject to change without notice. performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when in stalled in customer products. the informa tion contained herein is provided without re presentation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of idt?s products for any partic ular purpose, an implied warranty of merc hantability, or non-infringement of the in tellectual property rights of others. this document is presented only as a guide and does not convey any license under intellectual property rights of idt or any third parties. idt?s products are not intended for use in applications involvi ng extreme environmental conditions or in life support systems o r similar devices where the failure or malfunction of an idt product can be reasonably expected to signif- icantly affect the health or safety of users. anyone using an idt product in such a manner does so at their own risk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are registered tr ademarks of idt. other trademarks and service marks used he rein, including protected names, logos and designs, are the property of idt or their respective third party owners. copyright 2012. all rights reserved. 6024 silver creek valley road san jose, california 95138 sales 800-345-7015 (inside usa) +408-284-8200 (outside usa) fax: 408-284-2775 www.idt.com/go/contactidt technical support netcom@idt.com +480-763-2056 we?ve got your timing solution

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